1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to a content addressable memory (CAM) device and a method for repairing the CAM device.
2. Discussion of Related Art
In a random access memory (RAM) or a read only memory (ROM), an address is input to read data that is stored in a memory cell designated by the address. However, in a content addressable memory (CAM) device, external data is received and compared to stored data to determine whether it matches the stored data, and a signal corresponding to the comparing result is output. The signal corresponding to the comparing result may be in an address, pointer, or bit pattern form, which is referred to as “entry information”.
In the CAM device, each of the CAM cells includes a comparing circuit. External data input to the CAM device is compared to data stored in all the CAM cells, and the compared and output entry information becomes a result of a search operation. The CAM device is widely used as a tag memory for storing an address of a cache memory needing a high operation speed. Further, since the CAM device may be used to perform an address search, it is widely utilized to search a destination IP address in an Internet router.
CAM devices may be classified into binary CAMs and ternary CAMs depending on the characteristics of a CAM cell.
The binary CAM generally includes RAM cells each storing one of two logic states of data “1” and data “0”. The binary CAM further includes a comparing circuit. The comparing circuit compares external data (data for a search operation, hereinafter referred to as search data) to data stored in the RAM cell. If the search data matches the data stored in the RAM cell, the comparing circuit makes a corresponding match line at a certain logic state. Examples of the binary CAM are disclosed in U.S. Pat. Nos. 4,646,271 and 5,495,382.
The ternary CAM can store any one of three logic states, i.e., 0, 1 and don't care state. Examples of the ternary CAM are disclosed in U.S. Pat. Nos. 6,731,526 and 6,747,885.
In a read/write operation or a search operation of the CAM device, specific defective ones of a plurality of CAM cells constituting the CAM device may cause an error. Further, the defective cells may disable the operation of the CAM.
Other semiconductor memory devices having no search operation mode (e.g., SRAM and DRAM) generally include a redundant cell array substituting for the defective cell, in which data is stored in cells of the redundant cell array instead of the defective cells.
Conversely, since the CAM device has a search operation mode, factors other than the repair of other semiconductor memory devices having no search operation mode can be considered. That is, a unique repairing method can be used. There are, several methods for repairing a CAM device. Examples of the repair methods are disclosed in U.S. Pat. Nos. 6,445,628 and 6,275,406. Hereinafter, an example of a conventional method for repairing a CAM device will be described with reference to FIG. 1.
FIG. 1 is a block diagram illustrating an example of a method for repairing a conventional CAM device.
Referring to FIG. 1, a CAM array 10 in the CAM device includes a primary cell array 14, a primary encoder 24, a redundant cell array 12, and a redundant encoder 22.
The primary cell array 14 includes a plurality of entries E2, E4, E6, E8, E10, . . . , E12. Each of the primary entries E2 to E12 includes a plurality of CAM cells (not shown) for storing data. For example, the primary entry E2 includes a plurality of CAM cells that can store data bits such as 16 bits, 32 bits, 64 bits, and 128 bits. Each of the primary entries E2 to E12 is accessed as a primary address is input. In the primary cell array 14, L primary addresses are required to access L entries.
The redundant cell array 12 includes a plurality of redundant entries RE2, RE4, . . . , RE6. Each of the redundant entries RE2 to RE6 includes a plurality of CAM cells (not shown) for storing data. The redundant entries RE2 to RE6 store data in place of defective entries (including one or more defective cells) in the primary cell array 14. Each of the redundant entries RE2 to RE6 is accessed as a redundant address is input, similarly to the primary entries E2 to E12. In the redundant cell array 12, R redundant addresses are required to access R entries.
When one or more CAM cells in the primary cell array 14 are defective, primary entries including the defective cells may not be used to store data. For example, when the primary entries E8 and E10 respectively include defective cells DC1 and DC2, they may not be used to store data for operation of the CAM device. Here, the non-used primary entries E8 and E10 are defective entries. To store the data that is intended to be stored in the defective entries E8 and E10, the redundant entries RE4 and RE6 are activated instead of the defective entries E8 and E10.
The CAM device further includes a first address mapper 18, a fuse bank 30, a second address mapper 28, and a secondary encoder 26.
The fuse bank 30 stores addresses of the defective entries E8 and E10, which are the entries including the defective cells DC1 and DC2, and addresses of corresponding redundant entries so that entry information P_ADD generated by the primary encoder 24 and entry information R_ADD generated by the redundant encoder 22 are used for mapping.
For example, when the redundant entry RE4 is substituted for the defective entry E8 and the redundant entry RE6 is substituted for the defective entry E10, the addresses of the defective entries E8 and E10 and the corresponding redundant entries RE4 and RE6 are stored in the fuse bank 30. Here, the fuse bank 30 is fused by several methods to store addresses for address mapping. The fuse bank 30 is connected to the first and second address mappers 18 and 28 to provide the addresses stored in the fuse bank 30.
In read/write operation modes of the CAM device, the first address mapper 18 receives an n-bit read/write address R/W_ADD to perform read or write operation on the entries in the primary cell array 14. To determine whether the input read/write address R/W_ADD matches the addresses of the defective entries E8 and E10, the first address mapper 18 accesses the addresses of the defective entries E8 and E10 stored in the fuse bank 30. If the input read/write address R/W_ADD matches the addresses of the defective entries E8 and E10 stored in the fuse bank 30, the first address mapper 18 accesses the addresses of the redundant entries RE4 and RE6. The defective entries E8 and E10 are not read or written. Meanwhile, if the input read/write address R/W_ADD does not match the addresses of the defective entries E8 and E10 stored in the fuse bank 30, the read/write address R/W_ADD is sent to the CAM array 10 so that a primary entry designated by the read/write address R/W_ADD is accessed. The first address mapper 18 provides an (n+1)-bit address that is one-bit greater than an n-bit input address to the CAM array 10. One extra bit is provided to select one of the primary cell array 14 and the redundant cell array 12.
In the search operation mode of the CAM device, search data S_DATA is input to the CAM device, buffered by the search driver 16, and input to the CAM array 10. If the search data S_DATA is input to the CAM array 10, an entry storing data having the same pattern as the search data S_DATA is searched and a search result is sent to the encoder. If there are no defective entries, the redundant cell array 12 and thus the redundant encoder 22 are not used. However, when the defective entries E8 and E10 exist as shown in FIG. 1, the primary encoder 24 and the redundant encoder 22 may be both used. The primary encoder 24 and the redundant encoder 22 receive one or more search results from the primary cell array 14 and the redundant cell array 12, respectively. The data having the same pattern as the search data S_DATA may not exist in both the primary cell array 14 and the redundant cell array 12. In this case, a search result is not provided to both the primary encoder 24 and the redundant encoder 22. If the primary encoder 24 or the redundant encoder 22 receives two or more search results, the primary encoder 24 or the redundant encoder 22 outputs entry information P_ADD and R_ADD having the highest priority according to a defined priority.
In the search operation mode of the CAM device, when external search data S_DATA is provided and a search operation is performed, the CAM device searches entries that store data matching the search data from the primary cell array 14 or the redundant cell array 12. The result of a search in the primary cell array 14 or the redundant cell array 12 is provided to the primary encoder 24 or the redundant encoder 22. The entry information R_ADD generated by the redundant encoder 22 is loaded on a redundant entry information bus 32 and provided to the second address mapper 28. The second address mapper 28 maps the entry information R_ADD generated by the redundant encoder 22 to corresponding primary entry information (i.e., an address, pointer, or bit pattern of the defective entry). The primary entry information mapped to the entry information R_ADD generated by the redundant encoder 22 is provided to the secondary encoder 26. Further, the secondary encoder 26 receives entry information P_ADD on the primary entry information bus 34. The secondary encoder 26 outputs, via a result bus 36, final entry information E_RESULT 36 that is one of the primary entry information mapped to the entry information R_ADD and the entry information P_ADD sent by the primary entry information bus 34 according to the defined priority.
In the CAM device using the above-described repairing method, however, the defective entry participates in generating entry information at the primary encoder and unintended final entry information is output when search data match specific pattern data of the defective entry, due to a characteristic caused by a latch structure of a cell of a primary cell array, i.e., a characteristic of maintaining specific pattern data, even after substitution and repair into an entry in the redundant cell array so a defective entry does not participate in generating entry information.
Further, an example of conventional CAM devices includes a CAM device having an entry valid bit (EVB). The entry valid bit is for determining whether each entry in the primary cell array and the redundant cell array is used to generate final entry information. In particular, the CAM device having the entry valid bit can support a function of extending a search width in an Internet Protocol (IP) system of IPv6. Corresponding to such an extension of the search width, a CAM device having an EVB that realizes a function of determining whether to use the entry is expected to be propagated.
In the CAM device including the EVB, a defective entry does not participate in generating entry information at a primary encoder when an entry in a redundant cell array is substituted for a defective entry and the EVB is programmed to indicate that the entry in the redundant cell array substituting for the defective entry is valid. However, as the CAM cell of the primary cell array is formed in a latch structure, the defective entry participates in generating entry information at the primary encoder, which causes an operation error in the CAM device.